1. Field of the Invention
The present invention relates, generally, to a selectively transparent bus interface which enables one or more devices on a primary bus to communicate with a device on a secondary bus and, in one embodiment, to a primary bus to secondary bus selectively transparent interface with Hot Swap capability that does not incur the latency and performance degradation of conventional bridges.
2. Description of Related Art
The Peripheral Component Interconnect (PCI) bus is a common and integral part of modern computer systems. However, PCI bus systems are not physically well-suited for environments that require zero downtime for reconfiguration, or upgrades. The CompactPCI bus specification was developed to define a ruggedized version of the PCI bus for use in high reliability and availability systems. In a CompactPCI bus system, the bus is part of a powered backplane, and specialized circuit cards with staggered pins for the orderly application of power are coupled into the CompactPCI bus by insertion of the cards into slots on the backplane. One feature that the CompactPCI bus provides over a regular PCI bus is a Hot Swap feature, which is the ability to plug cards into and out of the backplane in a live (powered) environment, without having to turn off system power. Hot Swap is a term and definition governed by the CompactPCI specification, PICMG 2.1, R2.0, Jan. 17, 2001, incorporated herein by reference, which includes a definition of bits in a Hot Swap Register (HSR) used to perform Hot Swap operations.
As illustrated in the exemplary diagram of FIG. 1, as with a regular PCI bus, a CompactPCI bus 100 is typically part of a system which includes one or more processors or servers 102, main memory 104, Ethernet connections 106, bridges 108, adapter or interface cards 110, and the like. As with a regular PCI bus host, Standard Windows NT and Linux software can run on a CompactPCI bus host.
To implement Hot Swap capability, special circuitry is required in the hardware interface of the card, as well as system and card software drivers of cards that plug into the backplane. When a card is physically inserted or about to be extracted from a slot in the backplane, a latch on the card is closed or opened by an operator which triggers certain Hot Swap operations between the card and the host processor. These operations may load needed software drivers into host memory, or may delay the extraction of the card until all pending applications and transactions involving that card have been terminated.
Bridges are available on the market today which provide interface circuitry that performs the Hot Swap operations. However, these conventional bridges typically suffer from at least one or two performance drawbacks. First, some bridges with Hot Swap capability are non-transparent. Non-transparent bridges, as defined herein, occupy PCI configuration space and must be configured by the host before targets on the other side of the bridge can be accessed. In other words, the initiator must talk to the bridge before it can talk to the target device on the other side of the bridge. By comparison, transparent bridges occupy no configuration space, and thus only the target on the other side of the bridge needs to be addressed.
Second, conventional bridges suffer from poor data transfer rates. For example, conventional bridges with Hot Swap capability may produce a 30% performance degradation in the data transfer rates of PCI bus transactions. The performance degradation in conventional bridges is due in large part to the use of large first-in-first-out buffers (FIFOs) in data transfers. Conventional bridges utilize FIFOs to perform data transfers in two steps. For example, assume that an adapter card providing an interface to a fibre channel network is coupled to a secondary PCI bus. If the adapter card initiates a read data transaction from a target host processor on a primary PCI bus, an application specific integrated circuit (ASIC) resident on the adapter card may send the request to a bridge coupled to the secondary PCI bus, which will then forward the request to the host over the primary PCI bus. The bridge will then collect the data from the host in a FIFO within the bridge, and after some delay send the data back to the ASIC. This temporary accumulation of data in the FIFO is one source of delay. Another source of delay is the prefetching of expected data by the bridge. If the prefetched data turns out to be the wrong data, the data has to be discarded, creating additional delays.
The data transfer process of conventional bridges is illustrated in further detail in the example block diagram of FIG. 2. In the example of FIG. 2, a conventional bridge 200 may include a FIFO A 202 for receiving data from a secondary PCI bus 204, a state machine A 206 for handling secondary PCI bus protocols, and a register A 208 for meeting timing in the transfer of information from the secondary PCI bus to the primary PCI bus. The bridge 200 may also include a FIFO B 210 for receiving data from a primary PCI bus 212, a state machine B 214 for handling primary PCI bus protocols, and a register B 216 for meeting timing in the transfer of information from the primary PCI bus to the secondary PCI bus. In the example of FIG. 2, state machine A 206 handles PCI bus handshaking with devices on the secondary PCI bus 204, while state machine B 214 handles PCI bus handshaking with devices on the primary PCI bus 212. If, for example, an ASIC 218 on an interface card 220 initiates a transaction to write a block of data from its memory to host 222, the ASIC 218 sends a write request to the bridge 200 via secondary PCI bus 204. State machine A 206 responds to the ASIC 218 with the appropriate PCI protocol handshaking. ASIC 218 then starts filling FIFO A 202 with data. While FIFO A 202 is being filled with data, state machine B 214 arbitrates for access to the primary PCI bus 212. Data in FIFO A 202 is transmitted to the host 222 over the primary PCI bus 212 only after access to the primary PCI bus 212 is granted to the bridge.
This conventional approach simplifies the state machines because they have reduced functionality. State machine A 206 only interfaces with devices on the secondary PCI bus 204 and can start transactions even though the bridge 200 does not yet have access to the primary PCI bus 212. State machine B 214, working somewhat independently from state machine A 206, only interfaces with devices on the primary PCI bus 212 and can arbitrate for access to the primary PCI bus 212, regardless of the status of transactions on the secondary PCI bus 204. This is known as a loosely coupled interface, with transfers taking an unknown number of PCI clock cycles. Because these state machines need only worry about accesses to one bus, they are relatively simple and easy to implement from standardized ASIC libraries. Although the independence of the buses and the relative simplicity of the state machines is facilitated by use of the FIFOs, the FIFOs and the two-step data transfer process create transfer delays of potentially many PCI clock cycles.
Because the PCI bus has gained extensive acceptance in the marketplace, there are a number of products on the market today that implement a PCI bus interface in adapters for other peripheral buses and channels, such as a fibre channel network interface to be used in host bus adapter (HBA) designs for networking storage devices. FIG. 3 illustrates such an adapter in which a PCI bus 302 connects directly to a card 300 having an adapter ASIC 304 with a PCI bus interface, the ASIC 300 being further connected to a processor 306, memory 308, and an optics block 310 for interfacing to a fibre channel bus 312. However, such adapters do not have Hot Swap capability for interfacing to the CompactPCI bus.
Thus, a need exists for a PCI bus to CompactPCI bus selectively transparent interface circuit that provides Hot Swap capability without the latency and performance degradation of conventional bridges.